The present invention relates generally to bridges for interconnecting buses in a multiple bus computer environment, and more particularly to a bridge into which is incorporated a buffer for synchronizing operations of different data management protocols of the interconnected buses, thereby optimizing data transfer efficiency between the buses.
Computer systems or information handling systems typically include more than one bus, each bus in the system having devices attached thereto which communicate locally with each other over the bus. For example, a typical computer system includes a system bus or CPU Local Bus to which a central processing unit (CPU) is attached and over which the CPU communicates directly with other devices attached to the system bus. The system may also include one or more peripheral buses, which connect peripheral devices, such as input/output devices (I/O) and graphics packages, to the computer system.
Generally, system buses and peripheral buses use a different set of standard protocols or rules to conduct data transfers between the different devices and components connected to them. These protocols are designed into the bus and are referred to as the "architecture" of the bus. Accordingly, communication problems result when data must be transferred between a peripheral device connected to a peripheral bus and the CPU or another system component connected to the system bus. Since different bus architectures are involved in such a data transfer, data being transferred from the first bus architecture may not be in a form which is useable or intelligible by the receiving second bus architecture.
Thus, a mechanism is needed to "translate" data that is transferred from one bus architecture to another. This translation mechanism is normally contained in the hardware of a bus-to-bus bridge (interface) through which the two different buses are connected. The bus-to-bus bridge connecting a system bus to a peripheral bus is normally called a host bridge. Accordingly, the host bridge connecting a system bus and a peripheral bus contains all the logic and hardware that translates communications between the two buses and ensures that data is transferred between the two buses intelligibly.
To permit system-wide communication between devices on different buses, bus-to-bus bridges have been designed to match the communications protocol of one bus with that of another. Known bus-to-bus bridges include those disclosed in the following patent applications assigned to the IBM Corporation: U.S. patent application Ser. No. 07/815,992 entitled "BUS CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE"; U.S. Pat. No. 5,313,627 issued May 17, 1994 entitled "PARITY ERROR DETECTION AND RECOVERY"; U.S. patent application Ser. No. 07/816,204 entitled "CACHE SNOOPING AND DATA INVALIDATION TECHNIQUE"; U.S. Pat. No. 5,255,374 issued Oct. 19, 1993 entitled "BUS INTERFACE LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE"; U.S. patent application Ser. No. 07/816,691 entitled "BIDIRECTIONAL DATA STORAGE FACILITY FOR BUS INTERFACE UNIT"; U.S. patent application Ser. No. 07/816,693 entitled "BUS INTERFACE FOR CONTROLLING SPEED 0F BUS OPERATION"; U.S. Pat. No. 5,265,211 issued Nov. 23, 1993 entitled "ARBITRATION CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE"; and U.S. patent application Ser. No. 07/816,698 entitled "METHOD AND APPARATUS FOR DETERMINING ADDRESS LOCATION AT BUS TO BUS INTERFACE", all filed on Jan. 2, 1992. These applications describe mechanisms which permit system-wide communication of devices attached to different buses in the system.
Such bridges, however, do not solve the problems inherent with attempting to synchronize the inconsistent protocols of a system bus (such as an X86-type architecture bus) with a peripheral bus that uses Peripheral Component Interconnect (PCI) bus architecture or similar architectures. An example of such an inconsistency, is the different methods used by PCI buses and system buses to conduct a specialized data transfer called a sequential burst transfer.
A sequential burst transfer is a data transfer in which one address is provided during the address phase and several data phases occur thereafter. During the first data phase, the data is transferred into or out of the address provided in the address phase. During the subsequent data phases, the data transfers take place at the respective addresses that sequentially follow the address provided in the address phase (hereinafter sequential burst transfers shall be referred to simply as burst transfers).
The PCI burst protocol allows for the bursting of an unlimited number of data strings starting on any address boundary (assuming, of course, that PCI arbitration guidelines do not force the device initiating the burst to relinquish the bus). In contrast, the system bus burst protocol restricts the starting address for a burst transfer to certain address boundaries and allows only a certain number of data phases in a single burst transfer. Accordingly, the system bus architecture only permits a burst of four doublewords (DWORD's) or 16 bytes of data.
These restrictions in the system bus architecture, as well as others set forth below, require that the host bridge connecting a system bus and a PCI bus translate data transfers between the two different buses. The host bridge connecting a PCI bus to a system bus, however, must not only translate data between the two different architectures, but must perform this translation as efficiently as possible.
Thus, it is an object of the present invention to provide a bridge for interconnecting a CPU system bus and a bus that uses PCI bus architecture or a bus architecture having certain protocols that are similar to the PCI bus architecture in a multi-bus computer system while maximizing the data transfer efficiency between the interconnected buses.